Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be programmed with configuration data to provide various user-defined features. For example, desired functionality may be achieved by programming a configuration memory of a PLD with an appropriate configuration data bitstream.
Unfortunately, the transfer of such bitstreams to PLDs or external memory devices is often cumbersome. In particular, the loading of large uncompressed bitstreams can result in undesirable delays. For example, a bitstream of 10M bits sent through a serial interface operating at 10 MHz may require approximately 1 second to load, and an 80M bit bitstream may require approximately 8 seconds to load. Such delays can significantly affect the time required to power up PLDs during operation and testing. In addition, the use of large capacity boot ROMs to store uncompressed bitstreams can further increase system costs.
Various data compression methods have been developed to reduce these problems associated with uncompressed bitstreams. For example, in one approach, bulk erase bytes (i.e., bytes comprised of eight erase bits) appearing within an 8 byte sequence of configuration data may be represented by an 8 bit header identifying the location of the bulk erase bytes within the sequence. Nevertheless, the compression attainable from this approach is highly dependent on the presence of large sets of continuous bulk erase bytes.
In another approach, adaptive pattern recognition techniques may be used to identify repeated data patterns in a bitstream. The data patterns are associated with brief data codes stored in a mapping table embedded in the beginning of a compressed bitstream, or included as part of a configuration data file. A decompression engine may read the mapping table and use it to de-compress incoming data. However, this approach requires the additional overhead associated with building, sending, and processing the mapping table for each bitstream.
Accordingly, there is a need for an improved approach to the compression of configuration data bitstreams. In particular, there is a need for an approach that is well-suited for use with PLDs.